Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) and an asynchronous product term clock PTCLK. Each input macrocell has access toall four synchronous clocks.
Five pins on each member of the Ultra37000 family are desig-nated as input-only. There are two types of dedicated inputs on
Ultra37000 devices: input pins and input/clock pins. Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, double-regis-tered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control.
Figure 4 illustrates the architecture for the input/clock pins.
TSimilar to the input pins, input/clock pins can be combinatorial,u registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock
F path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is
available to all 16 macrocells. Each product term clock also supports user configurable polarity selection.
One of the most important features of the Ultra37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illus-trates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5 ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input setup time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless of the logic used.