• 时间:2012-05-24
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  Logic Block
  The logic block is the basic building block of the Ultra37000
  architecture. It consists of a product term array, an intelligent
  product-term allocator, 16 macrocells, and a number of I/O cells.
  The number of I/O cells varies depending on the device used.
  Refer to Figure 1 for the block diagram.
  Product Term Array
  Each logic block features a 72 x 87 programmable product term
  array. This array accepts 36 inputs from the PIM, which originate
  from macrocell feedbacks and device pins. Active LOW and
  active HIGH versions of each of these inputs are generated to
  create the full 72-input field. The 87 product terms in the array
  can be created from any of the 72 inputs.
  Of the 87 product terms, 80 are for general-purpose use for the
  16 macrocells in the logic block. Four of the remaining seven
  product terms in the logic block are output enable (OE) product
  terms. Each of the OE product terms controls up to eight of the
  16 macrocells and is selectable on an individual macrocell basis.
  In other words, each I/O cell can select between one of two OE
  product terms to control the output buffer. The first two of these
  four OE product terms are available to the upper half of the I/O
  macrocells in a logic block. The other two OE product terms are
  available to the lower half of the I/O macrocells in a logic block.
  The next two product terms in each logic block are dedicated
  asynchronous set and asynchronous reset product terms. The
  final product term is the product term clock. The set, reset, OE
  and product term clock have polarity control to realize OR
  functions in a single pass through the array.
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